1. Field of the Invention
The present invention relates to MOS switches and, more particularly, to a MOS switch that reduces clock feedthrough in a switched capacitor circuit.
2. Description of the Related Art
A MOS transistor is a device that controls a channel current, which flows from the drain to the source of the transistor, in response to a voltage applied to the gate of the transistor. As a result of this ability to control the channel current, MOS transistors are commonly used as voltage-controlled switches where the transistor provides a very-low resistance current path when turned on, and a very-high resistance current path when turned off.
FIGS. 1A-1B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional NMOS transistor 10. As shown in FIGS. 1A-1B, transistor 10 includes n+ spaced-apart source and drain regions 14 and 16 which are formed in a p-type substrate 12, and a channel region 18 which is defined between source and drain regions 14 and 16. In addition, transistor 10 also includes a dielectric layer 20 which is formed over channel region 18, and a gate 22 which is formed over dielectric layer 20.
In operation, when voltages are applied to source and drain regions 14 and 16 so that the drain-to-source voltage V.sub.DS is greater than zero, and a voltage is applied to gate 22 so that the gate-to-source voltage V.sub.GS is greater than the threshold voltage V.sub.T, transistor 10 turns on, thereby allowing a channel current I.sub.C to flow from drain region 16 to source region 14.
On the other hand, when the drain-to-source voltage V.sub.DS is greater than zero,. and a voltage is applied to gate 22 so that the gate-to-source voltage V.sub.GS is equal to or less than the threshold voltage V.sub.T, transistor 10 turns off, thereby preventing channel current I.sub.C from flowing from drain 16 to source 14 (except for a leakage current).
One of the most common applications for MOS switches, which are used in a wide variety of applications, is in a switched capacitor circuit. FIGS. 2A-2B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional switched capacitor circuit 50.
As shown in FIGS. 2A-2B, circuit 50 includes transistor 10 of FIG. 1 and a capacitor 52 which is connected between source region 14 and ground. In addition, drain region 16 is connected to receive an input signal V.sub.IN, while gate 22 is connected to receive a clock signal CLK.
In operation, when the drain-to-source voltage V.sub.DS is greater than zero, and the gate-to-source voltage V.sub.GS is greater than the voltage on the source region 14 by the threshold voltage V.sub.T, transistor 10 turns on. When transistor 10 turns on, a channel current I.sub.C flows from drain region 16 through source region 14 and charges up capacitor 52 to the voltage of the input signal V.sub.IN (assuming that the time that the clock signal CLK is high is much greater than the time constant defined by the turn-on resistance of transistor 10 and the capacitance of capacitor 52).
One drawback to the use of transistor 10 in switched capacitor circuit 50, however, is that the voltage applied to gate 22 via the clock signal CLK is capacitively coupled to source region 14 via a parasitic gate overlap capacitor C.sub.1 which is formed from gate 22, dielectric layer 20, and source region 14, and via a parasitic lateral fringing field capacitor C.sub.2 formed from gate 22, an insulation layer formed over source region 14, and source region 14.
This capacitive coupling, known as clock feedthrough, causes a small negative charge to accumulate at the surface of source region 14 below gate 22 (the lower plates of the parasitic capacitors C.sub.1 and C.sub.2), and a corresponding small positive charge to accumulate on the top plate of capacitor 52 when the clock voltage on gate 22 begins to rise, but is insufficient to turn on transistor 10 because the voltage on gate 22 is now greater than the voltage on source region 14.
Once the clock signal CLK turns transistor 10 on, capacitor 52, as noted above, charges up to the voltage of the input signal V.sub.IN. Since capacitor 52 charges up to the input voltage V.sub.IN, the small positive charge that accumulated on the top plate of capacitor 52 during the preturn-on period presents no problems.
The problem, however, comes after transistor 10 turns off. As the clock voltage on gate 22 continues to fall after transistor 10 has turned off, the capacitive coupling causes a small positive charge to accumulate at the surface of source region 14 below gate 22 (the lower plates of the parasitic capacitors C.sub.1 and C.sub.2), and a corresponding small negative charge to accumulate on the top plate of capacitor 52 because the voltage on gate 22 is now lower than the voltage on source region 14.
The small negative charge on the top plate of capacitor 52 functions as a negative offset voltage which, in turn, reduces the magnitude of the voltage held by capacitor 52. As a result, the voltage held by capacitor 52 at the end of the switched cycle erroneously represents the voltage of the input signal V.sub.IN by the small negative offset voltage.
One technique for reducing the negative offset voltage is to utilize a switched capacitor circuit with complementary MOS transistors. FIG. 3 shows a schematic diagram that illustrates a conventional switched capacitor circuit 70 that utilizes complementary MOS transistors.
As shown in FIG. 3, circuit 70 includes transistor 10 and capacitor 52 of FIGS. 2A and 2B, and a PMOS transistor 72. As shown, PMOS transistor 72 has a source 74 which is connected to drain 16 of transistor 10, a drain 76 which is connected to source 14 of transistor 10, and a gate 78 connected to receive an inverted clock signal /CLK.
In operation, when the clock signal CLK is high and the inverted clock signal /CLK is low, both transistors 10 and 72 are on. After transistors 10 and 72 turn off, the capacitive coupling of NMOS transistor 10 causes a small negative charge to accumulate on the top plate of capacitor 52, while PMOS transistor 72 causes of small positive charge to accumulate on the top plate of capacitor 52.
As a result, the negative charge that is injected onto the top plate of capacitor 52 by transistor 10 is theoretically cancelled out by the positive charge that is injected onto the top plate of capacitor 52 by transistor 72.
In actual practice, however, circuit 70 fails to completely remove the negative charge from capacitor 52 because the feedthrough parasitic capacitances of NMOS transistor 10 are typically not the same as the feedthrough parasitic capacitances of PMOS transistor 72.
In addition, the turn-on delays of NMOS transistor 10 and PMOS transistor 72 are not the same. As a result, the channel conductances of transistors 10 and 72 will typically not track each other during turn on and turn off. Thus, there is a need for a MOS switch that reduces clock feedthrough in a switched capacitor circuit.